A continuing trend in semiconductor technology is to build integrated circuits with more and/or faster semiconductor devices. The drive toward this ultra large-scale integration (ULSI) has resulted in continued shrinking of device and circuit features. To take advantage of increasing number of devices and to form them into one or more circuits, the various devices need to be interconnected.
To accomplish interconnection on such a small scale, a local interconnect is typically used within an integrated circuit to provide an electrical connection between two or more conducting or semi-conducting regions (e.g., active regions of one or more devices). For example, a plurality of transistors can be connected to form an inverting logical circuit using a local interconnect.
The local interconnect is typically a relatively low-resistance material, such as a conductor or doped semiconductor, that is formed to electrically couple the selected regions. For example, in certain arrangements, damascene techniques are used to provide local interconnects made of tungsten (W), or a like conductor, which is deposited within an etched opening, such as a via or trench that connects the selected regions together. The use of local interconnects reduces the coupling burden on the subsequently formed higher layers to provide such connectivity, which reduces the overall circuit size and as such tends to increase the circuit's performance. Accordingly, as the densities of the circuits increase there is a continuing need for more efficient, effective and precise processes for forming smaller local interconnects.
One critical factor in the fabrication of local interconnects is the alignment of the local interconnect with respect to other regions or areas of the semiconductor device(s). It is important to keep the local interconnect electrically isolated from those regions or areas that are not to be electrically connected via the local interconnect. For example, if a local interconnect is to be provided only to a drain region of a transistor arrangement, the local interconnect should be aligned such that the local interconnect does not electrically contact the transistor's gate conductor and/or source region. Controlling the alignment of the local interconnects during damascene formation can be challenging and the difficulty in doing so is increased as the critical dimensions of the device shrinks. Given the very small areas and regions in sub-quarter micron devices, the tolerance for proper alignment of the local interconnecting trenches or vias (i.e., etched openings) is extremely small. If a local interconnect is misaligned and accidentally contacts another area or region, then the device may fail to operate as required.
Thus, there is a continuing need for improved methods and arrangements for forming local interconnects, and in particular to prevent the local interconnects from electrically contacting the wrong areas or regions due to misalignment.